Slide 33 -
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Taiwan Semiconductor Manufacturing Company, Ltd. The Creator and Leader of the Foundry Industry TSMC Introduction
Market Overview
Technology Leadership
Capacity Leadership
Services Leadership
Introduction to TSMC - TSMC Is The Creator And Leader of the IC Foundry Industry
We are committed to leadership in capacity, technology and service
Founded in 1987 “Our vision is to be the most reputable, service-oriented maximum-total-benefits silicon foundry in the world, thereby earning the reward of also being the largest and most profitable foundry. To this end, we maintain a consistent focus on our foundry business, concentrating our commitment to being our customers’ “Virtual Fab”.
Dr. Morris Chang Chairman Taiwan Semiconductor Manufacturing Company, Ltd. TSMC Employee Growth TSMC Revenue 1992-2000(F) CAGR = 50% 4Q: NT$53.8 Bn
Year 2000 : NT$166.2 Bn 4Q
3Q
2Q
1Q NT $ M Source: Dataquest, TSMC Foundry Market Demand Foundry Market
Foundry Wafer B US$ M 8” eq. Wafers 1999 2000 2001 2002 2003 2004 35
30
25
20
15
10
5 35
30
25
20
15
10
5 Foundry 10-15% IDM Captive 85-90% TSMC 39% UMC 24% Chartered 8% IDM Foundry 20% Anam 3% Others 5% ~ U.S. $13.7 Billion TSMC: The Market Share Leader By Revenue (WW Foundry Industry,2000) Source: IC Insights, TSMC Normalized to TSMC wafer shipment excluding memory TSMC Leadership in Communications Source: Company News, TSMC 2001/Q1 TSMC Competitor 1 1 56% 26% Competitor 2 1
0 Sales by Market Segment Net Sales 50.2 73.1 28.3 31.8 47.5 53.9 166.2
(NT$Bn) Pre-merger) % of Sales System Co.
IDM
Fabless 1998 1999 1Q’ 00 2Q’ 00 3Q’ 00 4Q’ 00 2000 80%
60%
40%
20%
0%
Based on Quantity Sold at 8”equivalent Sales by Application Based on Quantity Sold at 8”equivalent 2000 3,408K 4Q’00 1,001K 3Q’00 942K Communications Consumer Others Memory Computer TSMC Leads in VDSM (0.25um & below)
Wafer Shipment in 2000 Normalized to TSMC Wafer shipment Source: Company News, TSMC Industry’s Leading Portfolio of Process Technologies
Logic Processes to 0.13um
Embedded Non-Volatile Memory to 0.18um
Mixed Signal & RF Processes
High Voltage Processes to 0.25um
Image Sensor Technology to 0.35um
Embedded DRAM to 0.25um
Copper and Low-K Dielectric Processes TSMC Is the Technology Leader TSMC: The R&D Investment Leader R&D R&D expense between 1992 and 1997 have not been restated under the current definition NT $ M TSMC Roadmap
Leading Foundry vs. SIA Roadmap Minimum Feature Size of Production TSMC SIA
Roadmap ’95 ’96 ’97 ’98 ’99 ’00 ’01 ’02 ’03 1
0.5
0.4
0.3
0.2
0.1 Excellent yield (lot average>92%) demonstrated for 4Mb
6T SRAM vehicle
More than a dozen customer tape-outs (LV,G,LP)
First in offering 0.13um CyberShuttle (Nov.00)
5 customers received functional devices in 1st
silicon (CPU,communications & FPGA)
First in starting 0.13um risk production (multiple customer
products-WIP greater than 3,000 wafers)
Deploying 0.13um manufacturing to 2 fabs in 2001,and to 6 fabs
in 2002 (incl. 300 fabs) with ample capacity to meet customer demand
0.13um Technology Leadership TSMC Logic Technology Features (Front End) 14 20 28.6 38 61 Gate delay ( ps/gate ) 17A 20A 32A 50A 70A Gate oxide thickness STI STI STI STI LOCOS Isolation SSR SSR SSR R well Diffused well Well formation Yes Yes Yes No No PSM ArF DUV-Scanner DUV-Scanner DUV-stepper I-Line Lithography 1.0V, 2.5V 1.2V, 3.3V 1.8, 3.3V 2.5, 3.3, 5V 3.3, 5V I/O Voltage 1.0V 1.2V 1.8V 2.5V 3.3V Core Voltage 8 7 6 5 4 # of metal layers Q4, 2000* Q1, 2000 Q1, 1999 Jan., 1998 Nov., 1996 Risk Production CL013 CL015 CL018 CL025 CL035 0.13 um 0.15 um 0.18 um 0.25 um 0.35 um Technology * For CL013G TSMC Logic Technology Features (Back End) 2.43 um2 3.42 um2 4.65 um2 7.56 um2 15.25 um2 Emb 6T SRAM cell Cu AlCu/Cu AlCu/Cu AlCu AlCu Metal Scheme Cu W CMP / Cu W CMP / Cu W CMP W E.B. Via Fill low K <= 2.9~3.6 low K <= 3.6 low K <= 3.7 Undoped Ox Undoped Ox Inter Metal Dielectric CoSi2 CoSi2 CoSi2 TiSi2 TiSi2 Silicide 8 7 6 5 4 # of metal layers Q4, 2000 Q1, 2000 Q1, 1999 Jan., 1998 Nov., 1996 Risk Production CL013 CL015 CL018 CL025 CL035 0.13 um 0.15 um 0.18 um 0.25 um 0.35 um TSMC Industry Leading Capacity (by Fab) 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000 ’90 ’92 ’94 ’96 ’98 ’00 ’02 ’04 Fab23 Fab22 Fab21 Fab20 Fab19 Fab18 Fab17 Fab16 Fab15 Fab14 Fab12 300PL SSMC WT VIS Fab8 Fab7 Fab6 Fab5 Fab4 Fab3 Fab2 Fab1 Note : Fab-1/2 : 6" Wafer Fab-3/4/5/6/7/8/VIS/WT/SSMC: 8" Wafer Fab12~23 and 300PL: 12" Wafer 2000-2005 Installed Capacity Plan Unit: K pcs, 8" Equivalent Wafer 374 528 680 844 1,206 1,212 163 99 228 Actual
Output 1,838 5,873 7,329 9,166 11,460 12”
Fab 8”
Fab 6”
Fab 1990-1999 Actual Output, 4,520 3,409 Installed
Plan TSMC Is The Capacity Leader In 2001 TSMC will continue to be the foundry industry’s
largest manufacturer of wafers But leadership is more than planned capacity
Flexibility
Timely expansion
Consistency across fabs The company has one 300mm pilot line running and
three full scale 300mm fabs under construction TSMC Industry Leading Capacity Plan (by Technology) Actual
Output Installed
Plan =0.07um =0.10um =0.13um =0.15um =0.18um <=0.25um <=0.35um <=0.5um 0.6um 0.8um >=1.0um >=2.0um 99 163 228 374 528 680 844 1,206 1,212 7,329 5,873 9,166 11,460 ’90 ’91 ’92 ’93 ’94 ’95 ’96 ’97 ’98 ’99 ’00 ’01 ’02 ’03 ’04 ’05 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000 Unit: K pcs, 8" Equivalent Wafer 1,838 3,409 4,520 Capacity by Fabs TSMC & Affiliates Installed Capacity: Annual (Monthly) FAB 1998 1999 2000 (8” equiv, k) FAB-1 FAB-2 FAB-3 FAB-4 FAB-5 FAB-8A Total Installed Capacity Annual Growth Rate FAB-8B WaferTech SSMC VIS FAB-6 FAB-7A FAB-7B 233.0 (19.6) 943.0 (79.0) 455.0 (39.0) 348.0 (31.0) 222.0 (28.0) 1,895 15% 154.0 (20.3) 0.0 205.0 (17.1) 936.0 (77.5) 524.0 (45.0) 426.0 (36.0) 417.0 334.0 3,409 80% 77.0 282.0 0.4 184.0 (39.0) (31.0) (17.0) (28.0) (32.0) ( 0.4) (22.0) 26.0 366.0 (44.0) (10.0) 0.0 0.0 0.0 0.0 252.0 (21.2) 940.0 (79.0) 478.0 (41.0) 353.0 (31.0) 116.0 (13.0) 1,644 38% 0.0 0.0 0.0 26.0 (8.0) 0.0 0.0 30.0 (9.0) 158.0 Total Installed Capacity Annual Growth Rate TSMC Emerging As Capacity Leader Year 2001 WW Total 88M Wafers (8”eq.) WW Total 79M Wafers (8”eq.) Year 2000 Source: Semico, SICAS, Dataquest, TSMC 3.4M(4.3%) TSMC ▲4.5M(5.2%) 5.1M(6.5%) Hyundai ▲5.4M(6.1%) 3.7M(4.7%) Intel ▲4.5M(5.1%) 4.1M(5.3%) Toshiba ▲4.3M(4.9%) 3.9M(5.0%) Samsung ▲4.3M(4.8%) 3.8M(4.8%) NEC ▲4.0M(4.6%) 2.5M(3.2%) STM ▲3.4M(3.9%) 3.7M(4.7%) Hitachi ▲3.8M(4.3%) 3.1M(4.0%) Philips ▲3.1M(3.6%) 2.4M(3.0%) UMC ▲2.8M(3.2%) 2.5M(3.1%) Motorola ▲2.7M(3.0%) 15.2M(19.3%) Others 16M((▼ 18.1%) TSMC Is The Foundry Industry Service Leader The Industry’s Leading Design Service Alliance
The Industry’s Leading Prototype Service, CyberShuttle
The Industry’s Award Winning Quality Assurance Program
The Industry’s Leading Mask Making Service
Turnkey Assembly and Test Services
The Industry Leader in Internet Services via eFoundry Suite …………………. TSMC Design Services EDA Alliances Technology Files, Design Kits Library / IP Alliances Library, Embedded Memory Service EDA Alliances Reference Flow IC Design Alliances Implementation Service Design Service Portal Prototype Verification Service Fab 1 Fab 2 Fab 3 Fab 4 Fab 5 Wafer
Tech Fab 6 Fab 7 Fab 11 Pure Foundry Service your Virtual Fab - Technology, Capacity, Service 3rd Party
Alliances TSMC
Services eFoundry™ Suite Close Collaboration in Design, Engineering and Logistics eFoundry™ Suite TSMC-Online TSMC- Direct TSMC-
YES TSMC-
Internet Layout Viewer TSMC-
eJobView Logistics Collaboration Engineering Collaboration Design Collaboration Design Collaboration Design Collaboration Engineering Collaboration Logistics Collaboration Engineering Collaboration eFoundry™ --- Your Virtual Fab TSMC-Online E-Commerce center for logistics, engineering and design collaboration TSMC-Direct System-to-system integration for collaborative planning and engineering data sharing TSMC-YES Collaborative yield enhancement effort between customers and TSMC engineering community TSMC-Internet Layout Viewer Web-based pre-tapeout design layout review between TSMC and customers TSMC-eJobView Web-based post-tapeout mask data inspection between TSMC and customers CyberShuttle Service
Reduced prototyping costs by as much as 10-fold.
Shorter prototyping time through expedited lot processing.
In-house backend ceramic packaging and bare die dicing service available
per customers’ request.
Broad spectrum of leading edge technologies with frequent launches: 0.25um down to 0.13um technology and derivatives such as RF,
mixed-signal, and embedded-flash technologies.
Frequent launches and dependable schedule announced in advance. Fast prototyping and shared cost : TSMC Quality Policy TSMC will strive to provide superior semiconductor manufacturing services for worldwide customers and establish mutually beneficial, long-term partnership.
TSMC will spread the dedication to quality throughout every facet of the company and achieve a culture of continual improvement to assure customer satisfaction. There is only one ultimate goal: Zero defect - in everything we do.
TSMC will adopt expedient containment programs to shield our customer from any insufficiency until each has been permanently corrected. We are responsible for and to each other regarding this goal. Reliability Assurance Process Monitor Process Qualification Build in Reliability All new technologies are developed according to “TSMC technology development methodology” which includes manufacturability verification (Cp/Cpk study), T0 pre-qualification plan and T1 qualification plan. All new technologies will be qualified prior to the mass production. Every released mature process will be monitored and reported on monthly basis to ensure TSMC wafers quality and reliability. Continuous improvement activities will be conducted as well. Technology Support Consult and support on reliability related design and application issue. Quality and Reliability Overview Manufacturing Technology
Development Product
Quality Gating Customer
Satisfaction Build In
Reliability Technology
Release
Qualification Incoming
Quality
Control Process
Reliability
Monitor In-Process
Quality
Control Outgoing
Quality
Assurance Backend
Quality
Assurance Customer
Satisfaction
Measurement
Program Customer
Corrective
Action
Response Product
Reliability
Monitor Total Quality Management Develop and integrate leading edge and cost effective wafer, test and assembly technologies. Assembly & Test Services Strategy Provide a seamless communication and data link throughout the entire assembly and test operation. Continuous quality and service improvement through internal monitoring and sound supplier management methodology. Quality & Engineering Assembly & Test Customer Benefits Single point responsibility from order to unit shipment
Complete WIP visibility throughout the entire process
Competitive cycle times from wafer start to unit ship
Proven drop ship system through fab, sort, assembly, and final test Competitive pricing
Reduced inventory cost
Advanced manufacturing services include mask making, wafer sort, assembly, and final test
TSMC extends QRA / test engineering / product engineering support to cover assembly and final test
Responsible for yield improvement and failure analysis
A single contact for engineering, quality, and reliability issues Service Cost Assembly Assembly & Test Capabilities Test Alliance with leading assembly houses
Mainstream and high-performance IC packaging
Reliability Qual Capability Digital, Mixed Signal, and Memory Test
In-House Wafer Sort and Probe Card Making and Maintenance
Alliance with Leading Test Subcontractors for Final Test Services
Test Program Correlation and Conversion
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