Doping Depositing impurities PowerPoint Presentation

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Doping: Depositing impurities into Si in a controlled manner Diffusion

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)`

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)`

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs)

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch)

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide

Slide 20 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm

Slide 21 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK

Slide 22 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput

Slide 23 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp

Slide 24 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer

Slide 25 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS

Slide 26 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas

Slide 27 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary

Slide 28 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant

Slide 29 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created

Slide 30 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+

Slide 31 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI

Slide 32 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer

Slide 33 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement)

Slide 34 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp)

Slide 35 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e-

Slide 36 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction)

Slide 37 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile

Slide 38 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem

Slide 39 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem Channeling OXIDE BLOCK 2. Dep amorphous material on the top It has to be very thin and not stop ions implant 3. Damage top of wafer and make it amorphous (eg high energy silicon implant)

Slide 40 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem Channeling OXIDE BLOCK 2. Dep amorphous material on the top It has to be very thin and not stop ions implant 3. Damage top of wafer and make it amorphous (eg high energy silicon implant) Channeling 4. Increase temperature ==> reduce channel cross section Channeling critical angle ~ (Z/E) 1/2 ==> Low energy implants more likely to channel

Slide 41 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem Channeling OXIDE BLOCK 2. Dep amorphous material on the top It has to be very thin and not stop ions implant 3. Damage top of wafer and make it amorphous (eg high energy silicon implant) Channeling 4. Increase temperature ==> reduce channel cross section Channeling critical angle ~ (Z/E) 1/2 ==> Low energy implants more likely to channel TED Transient Enhanced Diffusion Damage during implantation ==> point defects (vacancies) interstitial silicon atoms reduced during anneal Channel dopant diffuse to surface ==> VT modification ©Solid State Technology

Slide 42 -

Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem Channeling OXIDE BLOCK 2. Dep amorphous material on the top It has to be very thin and not stop ions implant 3. Damage top of wafer and make it amorphous (eg high energy silicon implant) Channeling 4. Increase temperature ==> reduce channel cross section Channeling critical angle ~ (Z/E) 1/2 ==> Low energy implants more likely to channel TED Transient Enhanced Diffusion Damage during implantation ==> point defects (vacancies) interstitial silicon atoms reduced during anneal Channel dopant diffuse to surface ==> VT modification ©Solid State Technology RTA Anneal to heal the damage Diffusion during anneal an issue High temp repair is faster than anneal Repair energy barrier 5 eV, diffusion barrier 3 or 4 eV 1. Adiabatic (laser, heats surface , < micro sec) profile control difficult (not used) 2. Thermal flux ( micro to 1 sec) laser, ebeam, flash lamp surface+bulk heating rapid cooling ==> point defects 3. Iso thermal (W-Halogen lamp) 30 sec (1100 C)

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Doping: Depositing impurities into Si in a controlled manner Diffusion Overview Diffusion vs Implantation Mechanism,Models Steps Equipment Goal: Controlled Junction Depth Controlled dopant concentration and profile Wafer (Substrate): P Type N “well” Preferred location of maximum concentration need not be the surface P+ P+ Source Drain Diffusion & Ion Implanatation Ion Implantation SOURCE Junction is where N = P Can also be used when doping N in N Bombardment of ions OXIDE BLOCK Wafer (Substrate)` Diffusion & Ion Implantation Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm Wafer (Substrate)` Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism Two ideal cases Constant source, limited source Using Fick’s First & second law J = Flux D - Diffusivity of A in B N- Concentration x - distance Models Constant Source Concentration at x=0 is No Complementary Error Function Total Dose Q Limited source Dose Q = constant Approx by Delta Fn Models Constant Source Concentration at x=0 is No 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt species, temp and time Models Limited Source Dose Q 2 1 3 N0 Distance from Surface Impurity Concentration Important Parameter : Dt Area under the curve is constant If you normalize, erfc drops faster than Gaussian Diffusivity Diffusivity Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit Solubility limit in the range of 10 20/cm3 at 1000o C Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs) Junction Formation N P Distance from surface Impurity Conc Carrier Conc Jn Diffusion: Drive In: Dopant re distribution Deposited dopant must be pushed into Si Re-distribution of dopant Oxidation of exposed Si to protect *Dopant profile changes due to diffusion * Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si Diffusion: Steps 2.HF Etch To remove oxide Not too much! 3.Deposit (pre dep) Deposit enough to be higher than the solubility limit 4.Drive In High temp to enable diffusion inside Si Also forms SiO2 (with high dopant concentration) 2-STEP diffusion (usual) 5.Deglaze (HF Etch) Oxide may act as dopant source in future steps Removing highly doped oxide may be problem (for dry etch) Diffusion: Dep: schematic Wafers are Horizontal Vertical Better Uniformity Less wafers per batch Poor Uniformity More wafers per batch (or can have smaller chamber) Dummy wafers placed in the beginning & end Gas Flow Gas Flow Doping: Gas phase Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form Chamber Reaction gas Carrier Gas (N2) + Source *Carrier gas may be bubbled through liquid source *Carrier gas may pass over heated solid source * inert gas can provide volume to maintain laminar flow Doping: Gas phase Phosphorus oxy chloride Phosphine Arsenic Oxide Diborane Boron Tribromide Reaction/Diffusion Limited Solid phase Solid Source Slugs between wafers Lower through put Cleaning is issue (slugs can break) Safer to handle(no toxic vapor at room temp) Spin coating (with solvents) Similar to photo resist coating Cost of extra spin/bake steps thickness variations Doping: Solid phase Boron Trioxide Tri Methyl Borate (TMB) Phosphorous pentoxide Arsenic Oxide Antimony Tri Oxide Issues Side diffusion Increases with temperature/time Limits the space between devices Maximum dopant concentration is near surface ==> majority of current near surface (Surface tends to have max defects) ==> less control Dislocation generation (thermal drive in) Surface contamination (dep) Low dopant concentration and thin junction (small junction depth) are difficult At 0.18 um , junction depth is ~ 40 nm At 0.09 um, junction depth may be 20 nm Issues: Side diffusion Side diffusion (Lateral Diffusion) OXIDE BLOCK Wafer (Substrate)` Diffusion BLOCK Example of Real systems : *Hitachi-Zestone VII *2m x 3m x 3m *300 mm wafer *one wafer at a time * lower thermal budget, * better control, uniformity * low throughput *Hitachi-Vertron V *1m x 3.5m x 3.3m *200 mm wafer *150 wafers at a time * higher thermal budget, * good control, uniformity * high throughput Example of Real systems : Protemp Gettering To remove unwanted impurities Try to get them to the back of wafer Defects Ar implant Dep SiN/SiO2 (stress) Oxygen during crystal growth (intrinsic) High Conc P on back of wafer Measurement Sheet Resistance (average) Four point probe, VDP (Van der Pauw) Bevel Interference Dye SIMS Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon sputtering deposits on the surface Used for controlled doping concentration profile (depth) Equipment Mechanism Issues Summary Equipment © Peter van Zant 1. Ion Source Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5) effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based Ionization chamber low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created 2. Analyzing Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio Some of the species from BF3 source Selection of B+ 3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric) Accln Energy Beam Current High Energy Low Energy Low Current High Current High Current Oxygen keV MeV 1 mA 10 mA 100 mA High energy ==> high throughput few seconds per wafer SOI 4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues: neutral atoms need to be removed because... dose calculated by current integrator Electrical (beam) scanning & Mechanical (wafer) scanning Beam Scan:(medium current) beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity Wafer scan: (high current) Beam shuttering: (electrical/mechanical) turn beam off when not on wafer 5. Target chamber End chamber low particle, high vacuum Wafer held on clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose For 2+ ions, divide by 2 and so on... Wafer charging: minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement) Mechanism Inelastic collision: Electron (ionization) Nuclear (nuclear reactions) Elastic collision Electron Nuclear (atom substitution) Electrons attract the +vely charged ions Nuclei repel the +vely charged ions At low energy Nuclear collisions predominant At high energy electronic collisions predominant Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp) Implantation Mask with Photoresist or oxide resist for medium and low energy, moderate dose high energy/high dose: increase in temp Resist re-flow Cross link (for organics) less soluble (stripping an issue) Faraday Cage Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias e- Issue: Transverse Straggle implant Even in implantation, dopants present in lateral direction OXIDE BLOCK Transverse Straggle (Diffraction) Channeling Some ions will move through “channels” without experiencing nuclear or electron collision for a “long” time ==> No Gaussian Profile Channeling 1. Hold the wafer at an angle (~ 8 degree) BLOCK Also causes “shadow” ==> increase transverse straggle(called undercut) Shadow Undercut ==> Too much angle is also a problem Channeling OXIDE BLOCK 2. Dep amorphous material on the top It has to be very thin and not stop ions implant 3. Damage top of wafer and make it amorphous (eg high energy silicon implant) Channeling 4. Increase temperature ==> reduce channel cross section Channeling critical angle ~ (Z/E) 1/2 ==> Low energy implants more likely to channel TED Transient Enhanced Diffusion Damage during implantation ==> point defects (vacancies) interstitial silicon atoms reduced during anneal Channel dopant diffuse to surface ==> VT modification ©Solid State Technology RTA Anneal to heal the damage Diffusion during anneal an issue High temp repair is faster than anneal Repair energy barrier 5 eV, diffusion barrier 3 or 4 eV 1. Adiabatic (laser, heats surface , < micro sec) profile control difficult (not used) 2. Thermal flux ( micro to 1 sec) laser, ebeam, flash lamp surface+bulk heating rapid cooling ==> point defects 3. Iso thermal (W-Halogen lamp) 30 sec (1100 C) Diffusion vs Ion Implantation Dep+Diffusion: depends on chemical nature and solubility Implantation: on energy of ion beam Expensive Better Control of junction depth, dose, profile Less ‘transverse straggle’